8 kb Pipelined Josephson-CMOS RAM
CMOS RAM for 4.2 K Operation With Josephson Digital Logic
3-stage pipeline, emphasis on data bandwidth
No high frequency clocks (125 MHz clocks)
Data rate dependent on generation of precise delays
Fast data read-outs (1-4 Gb/s)
Reduced number of Josephson sensors
Self-resetting MVTL OR gates with DC supplies
Simple interface circuits
Low active-power dissipation (10 mW)
Hybrid CMOS-Superconductor Interface Circuit
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