According to Rapid Single Flux Quantum (RSFQ) convention, "0" and "1" are the absence or presence of a Single Flux Quantum (SFQ) pulse within a certain time window. In the synchronous approach a global clock provides the timing information for the interpretation of the data. The real timing window is smaller than the clock cycle. In RSFQ integrated circuits, parameter variation can cause 15% change of gate delay. For ultimate performance of RSFQ Large Scale Integrated (LSI) circuits, the global synchronization approach cannot guarantee correct physical timing.
In the data-driven self-timed system, the timing information is carried by the data items themselves. Complementary data are transmitted between logic blocks through two parallel interconnections. When the data reach the following logic block, timing information can be recovered locally as a logical OR of the input complementary data, which generates a pulse for each data item. This is equivalent to a completion signal in the hand-shaking protocol. The timing signal is then distributed within the module just like a clock signal but is limited to a smaller region, and thus skew and racing can be controlled individually for each block. At the edge of this block, the complementary outputs can be generated easily by using a complementary D flip-flop, and the timing information will be carried forward.
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