Unlike reading a synchronous shift register with the high speed clock, DDST shift register can be read and reset by shifting in a stream of "0"s from the "input" terminal, or shifting in a stream of "1"s from the "complementary input" terminal. Thus an on-chip clock generator (CG) can be made to generate the "Read" signals, a stream of "1"s with a fixed number of bits.
The above figure shows a 4-bit clock generator design in which only the simplest asynchronous RSFQ circuits, such as JTL, pulse-splitter, and confluence-buffer, are used so as to avoid timing problems at high speed. Each bit consists one pulse-splitter, one confluence-buffer, and a few JTL's. The actual speed of the clock generator can be controlled by changing the dc bias so that it takes a certain delay for each clock pulse to come out, i.e., 50 ps delay for 20 GHz clock. In our design, the speed can be varied from 5 GHz to 40 GHz. This circuit has been redesigned for 50GHz operation.
High speed testing on a 32-bit clock generator has shown correct functions both in the time domain and in the frequency domain. To test the speed of the clock generator at lower speed, we trigger the clock generator at such a high speed that the clock generator only produces continious pulses; and at the output we put four T flip-flops and one SFQ/DC converter to reduce the output speed by a factor of 32. We can observed the speed of the output using either an oscilloscope or a spectrum analyzer. It is found correct that the speed of the output signal is not dependent on the frequency of the inital triggerring signal and is only dependent on the dc bias.
The above figure shows the test results of the dependence of the clock frequency on the dc bias voltage of the clock generator. The clock frequency ranges from 5 GHz to 38 GHz.
We have integrated this clock generation scheme with the shift register described in the previous section. This combination is a DDST high speed test system. It consists of two shift registers and one clock generator; the first shift register is loaded at low speed. When the first shift register is full, the shift registers are clocked at ultra-high-speed by the clock generator circuit. Finally, the data are recovered and analyzed at low speed. We have demonstrated this system at 20GHz. Our collaborator, Prof. Nobuyuki Yoshikawa at Yokohama National University has demonstrated a test of a 1:2 demultiplexer at 18GHz. We have redesigned the first system for 50GHz and will demonstrate a 2:1 dual-rail demultiplexer of a different type.
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DDST High Speed Testing System |
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