Rapid Single-Flux-Quantum (RSFQ) logic and memory, in which ones and zeros are represented by the presence or absence of single-flux-quantum pulses of few picosecond width, has the potential to be integrated into a general computing system with ultra-high speed (about 20 GHz) with the present niobium-based Josephson junction technology. However, timing of a large scale RSFQ integrated circuits at 20 GHz is a very critical problem faced by this technology.
A data-driven self-timing (DDST) scheme is proposed for RSFQ superconductive integrated circuits. In this asynchronous approach, the timing signals are generated from the data and no global clock is needed to drive the RSFQ circuit and system. The essence of the self-timing scheme is to localize the system timing in order to avoid the overhead of global clock distribution, and to minimize clock skew and racing. The data-driven self-timing scheme is applied to the design of a data-driven shift register, a self-timed demultiplexor, and a self-timed high speed digital testing system.
One circuit has been tested successfully up to 38 GHz. The measured bias margins for a 4-bit DDST shift register , a 4-bit clock generator , a 4-bit completion detector, and a Muller-C element are 16%, 11%, 23%, and 48%, respectively.
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