Figure shows one 4-bit shift register module consisting of one D flip-flop and three SR flip-flops. As one datum shifts in, a timing signal is generated and shifts every bit of the register forward by one bit. Reading of the DDST shift register can be done simply by shifting in new data bits or a stream of "0"s. Due to its nature of self-timing, the DDST shift register can handle input data and reading signals with either low speed or high speed such as 1 kHz or 20 GHz. This nature becomes even more important when a multiple speed system is necessary for RSFQ logic.
Construction of a longer DDST shift register based on the 4-bit module is straightforward since timing is localized inside the basic module and hazards due to clock skew and racing that usually happen in a long shift register can be avoided.
The picture (a) above shows the input "10110000" and the complementary
input "01001111" to the DC/SFQ converters. The picture (b) above
shows the output "00001011" and the complementary output "11110100"
from the SFQ/DC converters (Each transition corresponds one SFQ
pulse). Notice that the data have been shifted by 4 bits.
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